1. Field of the Invention
The present invention generally relates to integrated storage devices and more particularly to an improved dynamic random access memory dielectric structure.
2. Description of the Related Art
Dynamic random access memory (DRAM), is known to have a much higher memory density than static random access memory (SRAM) for the same chip area. To achieve high DRAM integration, either deep trench-capacitor or high-k dielectric stack-capacitor cells are commonly used. The deep trench capacitor has a planar surface topography, although the depth of the trench has become the limiting factor to prevent the scaling of DRAM exceeding 4Gb. Further, the high-k dielectric used in DRAMs is limited (mostly) by the material stability as well as the topography. The stack-capacitor is built on top of the silicon surface. The resulting non-planar surface has created problems for metallization as well as lithographic patterning. On the other hand, the performance of the DRAM that is determined by the drivability of MOS device is also now limited by the scaling.
As the channel width and oxide thickness of the devices cannot be reduced, the device performance begins to degrade. This becomes worse, when the Vdd (the power supply) level is also reduced. It is important that device performance must be maintained, so that DRAM access time, or cycle time can meet performance targets at low-power conditions. Fabrication steps to form trench or stack capacitor cell must be simple and have low-costs. Eventually, if DRAM cost cannot be reduced, the system of using large-volume DRAM will become expensive. In order for DRAM to completely replace the SRAM, not only does the density/area need to be improved, also the cost, power, and performance must all be attractive and competitive. Therefore, there is a need to reduce the cost and improve performance of DRAM.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional DRAM structures, the present invention has been devised, and it is an object of the present invention to provide a structure and method for an improved DRAM structure.
In order to attain the object(s) suggested above, the invention includes a method for simultaneously producing a dynamic random access memory device and associated transistor. More specifically, the method forms channel regions and capacitor openings in a substrate. Next, the invention forms capacitor conductors in the capacitor openings. Then, the invention simultaneously forms a single insulator layer above the channel regions and above the capacitor conductors. This single insulator layer comprises a capacitor node dielectric above the capacitor conductor and comprises a gate dielectric above the channel region.
In addition, the invention simultaneously patterns a single conductor layer above the single insulator layer. The single conductor layer forms a gate conductor above the gate dielectric and a ground plate above the capacitor node dielectric. In additional processing steps, the invention forms spacers on the gate conductor and the ground plate, dopes portions of the channel region to form source and drain regions (the drain region is in contact with the capacitor conductor), forms a covering insulator above the single conductor layer, and forms conductive contacts through the covering insulator to the source region.
The insulating substrate preferably includes shallow trench isolation regions below the capacitor conductors and the channel region preferably starts as a pure silicon region within the substrate. In addition, the single insulator layer preferably comprises an atomic level chemical vapor deposition process having molar ratios consistent with glass.
The invention also comprises a dynamic random access memory device that includes channel regions and capacitor conductors in a substrate. A single insulator layer is positioned above the channel regions and above the capacitor conductors. The single insulator layer comprises a capacitor node dielectric above the capacitor conductor and comprises a gate dielectric above the channel region. In addition, the invention includes a single conductor layer above the single insulator layer. The single conductor layer comprises a gate conductor above the gate dielectric and a ground plate above the capacitor node dielectric.
Further, there are spacers on the gate conductor and the ground plate, source and drain regions within the substrate (the source region is positioned on an opposite side of the gate conductor from the drain region). A covering insulator is positioned above the single conductor layer and conductive contacts extend through the covering insulator to the source region. The single insulator layer has molar ratios consistent with glass and maintains an amorphous state up to 1000xc2x0 C.
Thus, the invention forms high-k dielectrics in a single processing step for the transistor gate as well as the cell capacitor devices. This reduces the process cost, and also reduces the thermal budget seen while annealing the dielectric. The high-k dielectric used with the invention not only improves the transistor device performance, but also boosts the charge storage capability of the DRAM cells.